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item part number internal high-speed ram internal buffer ram internal expansion ram data memory 24 kb 32 kb 40 kb 48 kb 60 kb pd780053, 780053y pd780054, 780054y pd780055, 780055y pd780056, 780056y pd780058 none 1,024 bytes 1,024 bytes program memory (rom) 32 bytes data sheet description the pd780053, 780054, 780055, 780056, and 780058 (hereafter, referred to as pd78005x) are products of the pd780058 subseries in the 78k/0 series. the pd780053y , 780054y, 780055y, and 780056y (hereafter referred to as pd78005xy) are products of the pd780058y subseries in the 78k/0 series. these microcontrollers show a reduction in the emi (electro magnetic interference) noise generated internally compared to the conventional type, the pd78054 subseries. also they have provided is an 8-bit resolution a/d converter, 8-bit resolution d/a converter, timers, serial interfaces, real-time output ports, interrupt functions, and various other peripheral hardware. the pd780058y subseries is based on the pd780058 subseries but with the addition of an i 2 c bus interface function supporting multi-master. flash memory versions, the pd78f0058 and 78f0058y and various development tools are also available. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pd780058, 780058y subseries user? manual: u12013e 78k/0 series user? manual - instruction: u12326e features internal high-capacity rom & ram external memory expansion space: 64 kb minimum instruction execution time can be changed from high-speed (0.4 s) to ultra-low-speed (122 s) i/o ports: 68 (n-ch open-drain: 4) 8-bit resolution a/d converter: 8 channels (v dd = 1.8 to 5.5 v note ) 8-bit resolution d/a converter: 2 channels (v dd = 1.8 to 5.5 v note ) serial interface: 3 channels timer: 5 channels supply voltage: v dd = 1.8 to 5.5 v note the operation voltage of the a/d converter and d/a converter of the pd780058 is v dd = 2.7 to 5.5 v. mos integrated circuit 8-bit single-chip microcontrollers pd780053,780054,780055,780056,780058 780053y, 780054y,780055y,780056y the mark shows major revised points. document no. u12182ej3v0ds00 (3rd edition) date published march 2001 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1997, 2001
2 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds applications car audio systems, cellular phones, pagers, printers, av equipment, cameras, ppcs, vending machines, etc. ordering information part number package pd780053gc- -8bt 80-pin plastic qfp (14 14) pd780053gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780054gc- -8bt 80-pin plastic qfp (14 14) pd780054gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780055gc- -8bt 80-pin plastic qfp (14 14) pd780055gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780056gc- -8bt 80-pin plastic qfp (14 14) pd780056gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780058gc- -8bt 80-pin plastic qfp (14 14) pd780058gk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780053ygc- -8bt 80-pin plastic qfp (14 14) pd780053ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780054ygc- -8bt 80-pin plastic qfp (14 14) pd780054ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780055ygc- -8bt 80-pin plastic qfp (14 14) pd780055ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) pd780056ygc- -8bt 80-pin plastic qfp (14 14) pd780056ygk- -9eu 80-pin plastic tqfp (fine pitch) (12 12) remark indicates rom code suffix.
3 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries name. pd78054 with iebus tm controller. emi-noise reduced pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited function pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter control circuit and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780824 for automobile meter driver. on-chip dcan controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin pd780701y on-chip dcan/iebus controller 80-pin pd780833y on-chip controller compliant with j1850 (class2) pd780948 on-chip dcan controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 remark vfd (vacuum fluorescent display) is referred to as "fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
4 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds v dd min. value non-y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 2 ch 1 ch 8 ch 3 ch (time-division uart: 1ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1ch) 79 4.0 v interface supported pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1ch) 69 2.2 v control dash pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1ch) 56 4.0 v board control pd780824 32 k to 60 k 2 ch (uart: 1ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel the major functional differences among the subseries are listed below.
5 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds the major functional differences among the subseries are listed below. y subseries function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 88 1.8 v pd78070ay 61 2.7 v pd780018ay 48 k to 60 k 3 ch (i 2 c: 1ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time-division uart: 1 ch,i 2 c: 1 ch) 68 1.8 v pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, i 2 c: 1 ch) 69 2.7 v pd78054y 16 k to 60 k 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, i 2 c: 1 ch) 52 1.8 v pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, i 2 c: 1 ch) 51 pd780024ay 8 ch pd78018fy 8 k to 60 k 2 ch (i 2 c:1 ch) 53 lcd pd780308y 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch,i 2 c: 1 ch) 57 2.0 v drive pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) bus pd780701y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, i 2 c: 1 ch) 67 3.5 v interface supported pd780833y 65 4.5 v remark functions other than the serial interface are common to both the y and non-y subseries. v dd min. value
6 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds memory space general-purpose registers minimum instruction execution time instruction set i/o ports a/d converter operating voltage range d/a converter operating voltage range serial interface timers timer outputs clock output buzzer output test inputs supply voltage operating ambient temperature package overview of functions when main system clock is selected when subsystem clock is selected item product name pd780053 pd780054 pd780055 pd780056 pd780058 24 kb 32 kb 40 kb 48 kb 60 kb 1,024 bytes 32 bytes none 64 kb 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip minimum instruction execution time variable function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@5.0 mhz operation) 122 s (@32.768 khz operation) 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjust, etc. total: 68 cmos input : 2 cmos i/o : 62 n-ch open-drain i/o: 4 8-bit resolution 8 channels v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 ? 8-bit resolution 2 channels v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 ? 3-wire serial i/o/2-wire serial i/o/sbi note 1 /i 2 c bus note 2 mode selectable: 1 channel ? 3-wire serial i/o mode (automatic data transmit/receive function for up to 32 bytes provided on-chip): 1 channel ? 3-wire serial i/o/uart mode (time division transfer function provided on-chip) selectable: 1 channel ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel 3 (14-bit pwm output 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@5.0 mhz operation with main system clock) 32.768 khz (@32.768 khz operation with subsystem clock) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@5.0 mhz operation with main system clock) internal: 13, external: 6 internal: 1 1 internal: 1, external: 1 v dd = 1.8 to 5.5 v t a = ?0 to +85 c ? 80-pin plastic qfp (14 14) ? 80-pin plastic tqfp (fine pitch) (12 12) internal memory 1,024 bytes rom high-speed ram buffer ram expanded ram maskable non-maskable software vectored interrupt sources pd780053y pd780054y pd780055y pd780056y notes 1. pd78005x only 2. pd78005xy only
7 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds contents 1. pin configuration (top view) ........................................................................................... 8 2. block diagram ......................................................................................................................... 10 3. pin functions ............................................................................................................... ............. 11 3.1 port pins ............................................................................................................................... ................... 11 3.2 non-port pins ............................................................................................................................... .......... 13 3.3 pin i/o circuits and recommended connection of unused pins .................................................. 15 4. memory space ........................................................................................................................... 19 5. peripheral hardware function features ............................................................... 20 5.1 ports ............................................................................................................................... .......................... 20 5.2 clock generator ............................................................................................................................... ...... 21 5.3 timer/event counter .............................................................................................................................. 2 1 5.4 clock output controller ........................................................................................................................ 24 5.5 buzzer output controller ...................................................................................................................... 24 5.6 a/d converter ............................................................................................................................... .......... 25 5.7 d/a converter ............................................................................................................................... .......... 26 5.8 serial interfaces ............................................................................................................................... ...... 27 5.9 real-time output ports ......................................................................................................................... 29 6. interrupt and test functions ....................................................................................... 30 6.1 interrupt functions ............................................................................................................................... .30 6.2 test functions ............................................................................................................................... ......... 34 7. external device expansion function ......................................................................... 35 8. standby function ............................................................................................................ ....... 35 9. reset function ......................................................................................................................... 35 10. mask option ............................................................................................................................... .36 11. instruction set ............................................................................................................ ........... 37 12. electrical specifications .................................................................................................. 39 13. characteristics curves (reference values) ......................................................... 69 14. package drawings ................................................................................................................. 71 15. recommended soldering conditions ........................................................................... 73 appendix a. development tools .......................................................................................... 75 appendix b. related documents .......................................................................................... 78
8 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 1. pin configuration (top view) 80-pin plastic qfp (14 14) pd780053gc- -8bt, 780054gc- -8bt, 780055gc- -8bt, 780056gc- -8bt, 780058gc- -8bt, 780053ygc- -8bt, 780054ygc- -8bt, 780055ygc- -8bt, 780056ygc- -8bt 80-pin plastic tqfp (fine pitch) (12 12) pd780053gk- -9eu, 780054gk- -9eu, 780055gk- -9eu, 780056gk- -9eu, 780058gk- -9eu, 780053ygk- -9eu, 780054ygk- -9eu, 780055ygk- -9eu, 780056ygk- -9eu cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. [ ]: pd78005xy only 2. when the microcontroller is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 reset p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 p122/rtp2 p121/rtp1 p120/rtp0 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd0 p71/so2/txd0 p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb/txd1 p24/busy/rxd1 p25/si0/sb0 [/sda 0] p26/so0/sb1 [/sda 1] p27/sck0 [/scl] p40/ad0 p41/ad1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 v dd0 xt1/p07 xt2 ic x1 x2 v dd1 v ss0 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss1 p56/a14 p57/a15 p60 p61 p62 p63 p64/rd
9 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input ano0, ano1: analog output asck: asynchronous serial clock astb: address strobe av ref0 , av ref1 : analog reference voltage av ss : analog ground busy: busy buz: buzzer clock ic: internally connected intp0 to intp5: interrupt from peripherals p00 to p05, p07: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p72: port 7 p120 to p127: port 12 p130, p131: port 13 pcl: programmable clock rd: read strobe reset: reset rtp0 to rtp7: real-time output port rxd0, rxd1: receive data sb0, sb1: serial bus sck0 to sck2: serial clock scl: serial clock sda0, sda1: serial data si0 to si2: serial input so0 to so2: serial output stb: strobe ti00, ti01: timer input ti1, ti2: timer input to0 to to2: timer output txd0, txd1: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) pin identification
10 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 2. block diagram remarks 1. the internal rom and ram capacity varies depending on the product. 2. [ ]: pd78005xy only 16-bit timer/ event counter watchdog timer to0/p30 ti00/intp0/p00 ti01/intp1/p01 8-bit timer/ event counter 1 to1/p31 ti1/p33 8-bit timer/ event counter 2 to2/p32 ti2/p34 watch timer serial interface 0 si0/sb0[/sda0]/p25 so0/sb1[/sda1]/p26 sck0[/scl]/p27 serial interface 1 si1/p20 so1/p21 sck1/p22 stb/txd1/p23 serial interface 2 a/d converter av ss av ref0 ani0/p10 to ani7/p17 d/a converter av ss av ref1 ano0/p130, ano1/p131 intp0/p00 to intp5/p05 interrupt control buzzer output clock output control buz/p36 pcl/p35 v dd0 , v dd1 v ss0 , v ss1 ic ram 78k/0 cpu core rom port 0 p01 to p05 p00 p07 port 1 p10 to p17 port 2 p20 to p27 port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p60 to p67 port 7 p70 to p72 port 12 p120 to p127 port 13 p130, p131 external access ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 real-time output port rtp0/p120 to rtp7/p127 system control reset x1 x2 xt1/p07 xt2 busy/rxd1/p24 stb/txd1/p23 si2/rxd0/p70 so2/txd0/p71 sck2/asck/p72 busy/rxd1/p24
11 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds alternate function pin name i/o input only input input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o input only port 1 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software note 2 . i/o i/o port 2 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. port 3 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o i/o port 4 8-bit i/o port. input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. the test input flag (krif) is set to 1 by falling edge detection. 3. pin functions 3.1 port pins (1/2) intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 xt1 ani0 to ani7 si1 so1 sck1 stb/txd1 busy/rxd1 si0/sb0[/sda0] so0/sb1[/sda1] sck0 [/scl] to0 to1 to2 ti1 ti2 pcl buz ad0 to ad7 p00 p01 p02 p03 p04 p05 p07 note 1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 input function port 0 7-bit i/o port input input after reset input input input input notes 1. when using the p07/xt1 pins as an input port, set bit 6 (frc) of the processor clock control register (pcc) to 1. do not use the on-chip feedback resistor of the subsystem clock oscillator. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input pins, set port 1 to the input mode. at this time, on-chip pull-up resistors are automatically disconnected. remark [ ] pd78005xy only input
12 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds p50 to p57 p60 p61 p62 p63 p64 p65 p66 p67 p70 p71 p72 p120 to p127 p130, p131 3.1 port pins (2/2) alternate function function pin name i/o i/o i/o when used as an input port, an on-chip pull-up resistor can be specified by software. i/o i/o i/o n-ch open-drain input/ output port. an on-chip pull- up resistor can be specified by the mask option. leds can be driven directly. after reset port 5 8-bit i/o port. leds can be driven directly. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. port 6 8-bit i/o port. input/output can be specified in 1-bit units. port 13 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. port 12 8-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistor can be specified by software. port 7 3-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. input input input input input a8 to a15 rd wr wait astb si2/rxd0 so2/txd0 sck2/asck rtp0 to rtp7 ano0, ano1
13 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds alternate function function pin name i/o input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising edge and falling edges) can be specified. input serial interface serial data input output serial interface serial data output serial interface serial data input/output i/o i/o serial interface serial clock input/output input output input input output serial interface automatic transmit/receive busy input p00/ti00 p01/ti01 p02 p03 p04 p05 p25/sb0 [/sda0] p20 p70/rxd p26/sb1 [/sda1] p21 p71/txd p25/si0 [/sda0] p26/so0 [/sda1] p25/si0/sb0 p26/so0/sb1 p27 [/scl] p22 p72/asck p27/sck0 p23/txd1 p24/rxd1 p70/si2 p24/busy p71/so2 p23/stb p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p120 to p127 p40 to p47 input intp0 intp1 intp2 intp3 intp4 intp5 si0 si1 si2 so0 so1 so2 sb0 sb1 sda0 sda1 sck0 sck1 sck2 scl stb busy rxd0 rxd1 txd0 txd1 asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz rtp0 to rtp7 ad0 to ad7 output 16-bit timer (tm0) output (also used for 14-bit pwm output) 8-bit timer (tm1) output 8-bit timer (tm2) output clock output (for trimming of main system clock and subsystem clock) buzzer output real-time output port from which data is output in synchronization with a trigger lower address/data bus for expanding memory externally output output output after reset input input input input input input input input input input input input input asynchronous serial interface serial data output asynchronous serial interface serial data input asynchronous serial interface serial clock input external count clock input to the 16-bit timer (tm0) capture trigger signal input to the capture register (cr00) external count clock input to the 8-bit timer (tm1) external count clock input to the 8-bit timer (tm2) pd78005xy only pd78005xy only i/o serial interface automatic transmit/receive strobe output input input input remark [ ]: pd78005xy only 3.2 non-port pins (1/2)
14 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 3.2 non-port pins (2/2) alternate function function pin name i/o after reset input input input output input output input input input input input wait astb ani0 to ani7 ano0, ano1 av ref0 av ref1 av ss reset x1 x2 xt1 xt2 v dd0 v ss0 v dd1 v ss1 ic wait insertion at external memory access strobe output that externally latches address information output to ports 4 and 5 to access external memory. a/d converter analog input d/a converter analog output a/d converter reference voltage input (also used for analog power supply) d/a converter reference voltage input a/d converter and d/a converter ground potential use at the same potential as v ss0 . system reset input connecting crystal resonator for main system clock oscillation connecting crystal resonator for subsystem clock oscillation port block positive power supply port block ground potential positive power supply (except for port and analog blocks) ground potential (except for port and analog blocks) internally connected. connect directly to v ss0 or v ss1 . p66 p67 p10 to p17 p130, p131 p07 input input input input input a8 to a15 rd wr output output higher address bus for expanding memory externally strobe signal output for reading from external memory strobe signal output for writing to external memory p50 to p57 p64 p65
15 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, see figure 3-1. table 3-1. pin i/o circuit type (1/2) i/o circuit type 2 8-c 16 11-d 8-c 5-h 8-c 5-h 8-c 10-b 5-h 8-c 5-h 5-n 5-h 13-j 5-h input i/o input i/o connect to v ss0 . input: independently connect to v ss0 via a resistor. output:leave open. connect to v dd0 . p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb/txd1 p24/busy/rxd1 p25/si0/sb0 [/sda0] p26/so0/sb1 [/sda1] p27/sck0 [/scl] p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb pin name i/o recommended connection input: independently connect to v dd0 or v ss0 via a resistor. output: leave open. input: independently connect to v dd0 via a resistor. output: leave open. input: independently connect to v dd0 or v ss0 via a resistor. output: leave open. input: independently connect to v dd0 via a resistor. output: leave open. input: independently connect to v dd0 or v ss0 via a resistor. outpu: leave open. remark [ ]: pd78005xy only.
16 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds table 3-1. pin i/o circuit type (2/2) i/o circuit type p70/si2/rxd0 p71/so2/txd0 p72/sck2/asck p120/rtp0 to p127/rtp7 p130/ano0, p131/ano1 reset xt2 av ref0 av ref1 av ss ic pin name i/o recommended connection 8-c 5-h 8-c 5-h 12-c 2 16 i/o input input: independently connect to v ss0 via a resistor. output: leave open. leave open. connect to v ss0 . connect to v dd0 . connect to v ss0 . directly connect to v ss0 or v ss1 . input: independently connect to v dd0 or v ss0 via a resistor. output: leave open.
17 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 3-1. pin i/o circuits (1/2) type 2 in type 8-c pull-up enable data output disable v dd0 p-ch v n-ch p-ch in/out ss0 v ss0 v ss0 v ss0 v ss0 v ss0 v dd0 type 10-b enable type 11-d pull-up enable data output disable v dd0 p-ch n-ch p-ch in/out v dd0 type 5-h input enable type 5-n pull-up enable data output disable v dd0 p-ch n-ch p-ch in/out v dd0 schmitt-triggered input with hysteresis characteristics pull-up enable data output disable in/out n-ch v ref input (threshold voltage) v dd0 p-ch n-ch p-ch v dd0 p-ch + ? comparator pull-up enable data output disable v p-ch n-ch p-ch in/out dd0 v dd0 open drain
18 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 3-1. pin input/output circuits (2/2) type 12-c type 16 pull-up enable data output disable v dd0 p-ch n-ch p-ch in/out v ss0 v ss0 v ss0 v dd0 n-ch input enable type 13-j data output disable n-ch p-ch in/out v dd0 v dd0 rd mask option middle-voltage input buffer p-ch analog output voltage xt1 feed back cut-off xt2 p-ch
19 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 4. memory space figure 4-1 shows the memory map of the pd78005x and 78005xy. figure 4-1. memory map notes 1. pd780058 only 2. if external device expansion functions are to be employed for the pd780058, set the size of the internal rom to 56 kb or less using internal the memory size switching register (ims). 3. the internal rom capacity depends on the product (see the table below). last address of internal rom nnnnh part number pd780053, 780053y pd780054, 780054y pd780055, 780055y pd780056, 780056y pd780058 5fffh 7fffh 9fffh bfffh efffh special function registers (sfrs) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram reserved internal buffer ram 32 8 bits reserved external memory internal rom note 3 data memory space program memory space ffffh ff00h feffh fee0h fedfh fb00h faffh fae0h fadfh fac0h fabfh fa80h fa7fh nnnnh + 1 nnnnh 0000h reserved internal expanded ram 1,024 8 bits reserved note 2 fa7fh f800h f7ffh f400h f3ffh f000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h note 1
20 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 5. peripheral hardware function features 5.1 ports the following three types of i/o ports are available. cmos input (p00, p07): 2 cmos i/o (p01 to p05, port 1 to port 5, p64 to p67, port 7, port 12, port 13): 62 n-ch open-drain i/o (p60 to p63): 4 total: 68 table 5-1. port functions pin name function input only i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. the test flag (krif) is set to 1 by falling edge detection. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. leds can be driven directly. n-ch open-drain i/o port. input/output can be specified in 1-bit units. on-chip pull-up resistor can be used by mask option. leds can be driven directly. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip pull-up resistor can be specified by software. port name port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p63 p64 to p67 p70 to p72 p120 to p127 p130, p131 p00, p07 p01 to p05
21 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 5.2 clock generator two types of generators, a main system clock generator and a subsystem clock generator, are available. the minimum instruction execution time can be changed. ?0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@5.0 mhz operation with main system clock) ?122 s (@32.768 khz operation with subsystem clock) figure 5-1. clock generator block diagram 5.3 timer/event counter five timer/event counter channels are incorporated. ?16-bit timer/event counter: 1 channel ?8-bit timer/event counter: 2 channels ?watch timer: 1 channel ?watchdog timer: 1 channel table 5-2. operations of timer/event counter 16-bit timer/ event counter watch timer watchdog timer external event counter operation mode timer output pwm output square wave output pulse width measurement interrupt request function interval timer one-shot pulse output 8-bit timer/ event counter 1 channel 1 channel 1 output 1 output 1 input 1 output 1 output 2 2 channels 2 channels 2 outputs 2 outputs 2 1 channel 2 1 channel 1 xt1/p07 xt2 x1 x2 f xt f xx subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx f xt 2 prescaler selector selector f x f x 2 stop scaler 2 1
22 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 5-2. block diagram of 16-bit timer/event counter figure 5-3. block diagram of 8-bit timer/event counter internal bus 8-bit compare register (cr10) 8-bit timer counter 1 (tm1) clear match selector output controller output controller inttm1 to2/p32 inttm2 to1/p31 clear match selector selector selector selector 8-bit compare register (cr20) 8-bit timer counter 2 (tm2) internal bus f x /2 f xx /2 to f xx /2 9 11 ti1/p33 f xx /2 to f xx /2 f x /2 9 11 ti2/p34 internal bus selector selector 16-bit timer counter (tm0) clear output controller pwm pulse output controller 16-bit capture/ compare register (cr00) internal bus intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/intp1 watch timer output 2f xx f xx f xx /2 2 f xx /2 ti00/p00/intp0 16-bit capture/ compare register (cr01) edge detector match match selector
23 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 5-4. block diagram of watch timer figure 5-5. block diagram of watchdog timer controller 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector 2 4 2 5 2 6 2 7 2 8 2 9 2 11 2 f xx 3 f xx f xx f xx f xx f xx f xx f xx inttm3 intwt 5-bit counter prescaler selector selector selector selector f xx /2 f xt 7 f w 2 f 4 2 5 2 6 2 7 2 8 2 9 2 14 2 13 to 16-bit timer/ event counter w f w f w f w f w f w f w f w
24 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 5.4 clock output controller clocks with the following frequencies can be output as the clock output. 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (@5.0 mhz operation with main system clock) 32.768 khz (@32.768 khz operation with subsystem clock) figure 5-6. block diagram of clock output controller 5.5 buzzer output controller clocks with the following frequencies can be output as the buzzer output. ?1.2 khz/2.4 khz/4.9 khz/9.8 khz (@5.0 mhz operation with main system clock) figure 5-7. block diagram of buzzer output controller selector synchronization circuit output controller pcl/p35 f xx f xx f xx f xx f xx f xx /2 /2 2 /2 3 /2 4 /2 5 f xx /2 6 f xx f xt /2 7 selector output controller buz/p36 f xx /2 9 f xx /2 10 f xx /2 11
25 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 5.6 a/d converter an a/d converter consists of eight 8-bit resolution channels is incorporated. the following two types of the a/d conversion operation startup methods are available. ?hardware start ?software start figure 5-8. block diagram of a/d converter tap selector intad intp3 internal bus av ref0 (funcitons alternately as analog power supply) av ss av ss a/d conversion result register (adcr) controller succesive approxmation register (sar) edge detector ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 selector sample & hold circuit voltage comparator series resistor string
26 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds n = 0, 1 m = 4, 5 x = 1, 2 5.7 d/a converter a d/a converter consisting of two 8-bit resolution channels is incorporated. the conversion method is the r-2r resistor ladder method. figure 5-9. d/a converter block diagram internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss damm inttmx dacsn write anon d/a converter mode register
27 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 5.8 serial interfaces three clocked serial interface channels are incorporated. ?serial interface channel 0 ?serial interface channel 1 ?serial interface channel 2 table 5-3. types and functions of serial interface function 3-wire serial i/o mode with automatic transmit/receive function sbi (serial bus interface) mode 2-wire serial i/o mode 3-wire serial i/o mode (msb/lsb first switching possible) (msb/lsb first switching possible) (msb first) (msb first) (on-chip dedicated baud rate generator) serial interface channel 0 pd78005x pd78005xy serial interface channel 1 serial interface channel 2 (msb/lsb first switching possible) (msb/lsb first switching possible) asynchronous serial interface (uart) mode (on-chip time division transfer function) i 2 c bus mode (msb first) figure 5-10. block diagram of serial interface channel 0 (1/2) (a) pd78005x busy/acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter bus release/command/ acknowledge detector serial clock controller selector selector selector si0/sb0/p25 so0/sb1/p26 sck0/p27 intcsi0 to2 f xx /2 to f xx /2 8
28 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 5-10. block diagram of serial interface channel 0 (2/2) (b) pd78005xy figure 5-11. block diagram of serial interface channel 1 internal bus interrupt request signal generator handshake controller buffer ram serial clock controller selector serial clock counter serial i/o shift register 1 (sio1) automatic data transmit/ receive address pointer (adtp) automatic data transmit/receive interval specification register (adti) 5-bit counter intcsi1 f xx /2 to f xx /2 to2 8 si1/p20 so1/p21 stb/txd1/p23 busy/rxd1/p24 sck1/p22 match acknowledge output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter start condition/stop condition/acknowledge detector serial clock controller selector selector selector si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 intcsi0 to2 f xx /2 to f xx /2 8
29 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 5-12. block diagram of serial interface channel 2 5.9 real-time output ports data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt request and external interrupt request generation in order to output off-chip. this is the real-time output function. pins used to output off-chip are called real-time output ports. by using a real-time output port, a signal with no jitter can be output. this is most applicable to control of stepper motors, etc. figure 5-13. block diagram of real-time output port rxd0/si2/p70 rxd1/busy/p24 selector asck/sck2/p72 intser intsr/intcsi2 intst f xx to f xx /2 10 internal bus receive buffer register (rxb/sio2) direction controller receive shift register (rxs) receive controller direction controller transmit shift register (txs/sio2) transmit controller sck output controller baud rate generator txd0/so2/p71 txd1/stb/p23 selector internal bus p127 p120 output latch real-time output buffer register higher 4 bits (rtbh) real-time output buffer register lower 4 bits (rtbl) real-time output port mode register (rtpm) output trigger controller intp2 inttm1 inttm2
30 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds non-maskable: 1 maskable: 19 software: 1 table 6-1. interrupt source list (1/2) interrupt type note 1 default priority name watchdog timer overflow (with watchdog timer mode 1 selected) interrupt source trigger watchdog timer overflow (with interval timer mode selected) 1 2 3 4 5 6 7 8 9 10 11 intp0 intp1 intp2 intp3 intp4 intp5 intcsi0 intcsi1 intser intsr intcsi2 intst 0006h 0008h 000ah 000ch 000eh 0010h 0014h 0016h 0018h 001ah 001ch (c) internal/ externa vector table address basic configuration type note 2 intwdt non-maskable (a) internal 0004h 0 intwdt (b) pin input edge detection external maskable (b) (d) 6. interrupt and test functions 6.1 interrupt functions the interrupt function includes, three different kinds of interrupts from 21 sources, as shown below. end of serial interface channel 0 transfer end of serial interface channel 1 transfer occurrence of serial interface channel 2 uart reception error end of serial interface channel 2 uart reception end of serial interface channel 2 3-wire transfer end of serial interface channel 2 uart transmission notes 1. default priority is the priority order when several maskable interrupt requests are generated simultaneously. 0 is the highest order and 17 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1. remark there are two types of interrupt source for the watchdog timer: non-maskable interrupts and maskable interrupts (internal). only one of these interrupts can be selected. internal
31 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds table 6-1. interrupt source list (2/2) name interrupt source reference time interval signal from watch timer generation of match signal of 16-bit timer counter and capture/compare register (cr00) generation of match signal of 16-bit timer counter and capture/compare register (cr01) generation of match signal of 8-bit timer/event counter 1 generation of match signal of 8-bit timer/ event counter 2 end of conversion by a/d converter execution of brk instruction 17 intad brk 0028h 003eh (e) notes 1. default priority is the priority order when several maskable interrupt requests are generated simultaneously. 0 is the highest order and 17 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1. interrupt type software 12 inttm3 001eh (b) internal/ externa vector table address basic configuration type note 2 trigger 13 inttm00 0020h internal inttm01 14 0022h inttm1 15 0024h inttm2 16 0026h note 1 default priority maskable
32 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus priority controller vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detector sampling clock internal bus standby release signal interrupt request
33 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mk ie pr isp if priority controller vector table address generator external interrupt mode register (intm0) edge detector internal bus standby release signal interrupt request priority controller vector table address generator internal bus interrupt request
34 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 6.2 test functions the test function includes the two test input sources shown in table 6-2 below. table 6-2. test input source list internal/external name intpt4 intwt watch timer overflow port 4 falling edge detection internal external test input source trigger figure 6-2. basic configuration of test function if: test input flag mk: test mask flag if mk internal bus test input flag standby release signal
35 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 7. external device expansion function the external device expansion function connects external devices to areas other than the internal rom, ram, and sfr areas. ports 4 to 6 are used for external device connection. 8. standby function the following two standby functions are available for further reduction of system current consumption. ? halt mode: in this mode, the cpu operating clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. ? stop mode: in this mode oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. figure 8-1. standby function note the current consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set the mcc (bit 7 of the processor clock control register (pcc)) to stop the main system clock. the stop instruction cannot be used. caution when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark css: bit 4 of the processor clock control register (pcc). 9. reset function the following two reset methods are available. external reset by reset signal input internal reset by watchdog timer program loop time detection main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation continues) subsystem clock operation note halt mode note (clock supply to cpu is stopped, oscillation continues) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css = 1 css = 0
36 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 10. mask option the pd78005x and 78005xy have the following mask options. pull-up resistor an on-chip pull-up resistor for p60 to p63 (i/o port) can be specified in 1-bit units. <1> specifies on-chip pull-up resistor. <2> does not specify on-chip pull-up resistor.
37 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 11. instruction set (1) 8-bit instructions mov, xch, add addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
38 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (2) 16-bit instructions mov, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de, or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw xchw rp note sfrp movw saddrp movw !addr16 movw sp movw none incw decw push pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz
39 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ?.3 to +6.5 v av ref0 ?.3 to v dd + 0.3 v av ref1 ?.3 to v dd + 0.3 v av ss ?.3 to +0.3 v input voltage v i1 p00 to p05, p07, p10 to p17, p20 to p27, p30 to p37, ?.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63 n-ch open drain ?.3 to +16 v output voltage v o ?.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss ?0.3 to av ref0 + 0.3 v output i oh per pin ?0 ma current, high total for p01 to p05, p30 to p37, p56, p57, p60 to p67, ?5 ma p120 to p127 total for p10 to p17, p20 to p27, p40 to p47, ?5 ma p50 to p55, p70 to p72, p130, p131 output i ol note per pin peak value 30 ma current, low rms value 15 ma total for p50 to p55 peak value 100 ma rms value 70 ma total for p56, p57, p60 to p63 peak value 100 ma rms value 70 ma total for p10 to p17, p20 to p27, peak value 50 ma p40 to p47, p70 to p72, p130, p131 rms value 20 ma total for p01 to p05, p30 to p37, peak value 50 ma p64 to p67, p120 to p127 rms value 20 ma operating ambient t a ?0 to +85 c temperature storage t stg ?5 to +150 c temperature note the rms value should be calculated as follows: [rms value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
40 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds main system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) recommended circuit typ. max. 5.0 4 5.0 10 30 5.0 500 unit mhz ms mhz ms mhz ns resonator ceramic resonator crystal resonator external clock parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high-/low-level width (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 1.0 1.0 conditions v dd = oscillation voltage range after v dd reaches oscillation voltage range min. x1 ic x2 c1 c2 x1 ic x2 c1 c2 x1 x2 pd74hcu04 1.0 85 v dd = 4.5 to 5.5 v
41 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p01 to p05, p10 to p17, 15 pf capacitance unmeasured pins returned p20 to p27, p30 to p37, to 0 v. p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 p60 to p63 20 pf remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. subsystem clock oscillator characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) min. 32 32 5 notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage min. resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions v dd = 4.5 to 5.5 v typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz s cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. recommended circuit remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 ic xt2 c4 c3 r2 xt1 xt2 pd74hcu04
42 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, 0.8v dd v dd v p120 to p127, p130, p131 v ih2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8v dd v dd v p33, p34, p70, p72, reset 0.85v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7v dd 15 v (n-ch open drain) 0.8v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd ?0.5 v dd v v dd ?0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v note 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, 0 0.2v dd v p120 to p127, p130, p131 v il2 p00 to p05, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2v dd v p33, p34, p70, p72, reset 0 0.15v dd v v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.5 v 0 0.2v dd v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v note 0 0.1v dd v output voltage, v oh v dd = 4.5 to 5.5 v, i oh = ? ma v dd ?1.0 v high i oh = ?00 av dd ?0.5 v output voltage, v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v low i ol = 15 ma p01 to p05, p10 to p17, p20 to v dd = 4.5 to 5.5 v, 0.4 v p27, p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67, p70 to p72, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v open drain, pulled-up (r = 1 k ? ) v ol3 i ol = 400 a 0.5 v note when p07/xt1 pin is used as p07, the inverse phase of p07 should be input to xt2 pin using an inverter. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
43 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p05, p10 to p17, p20 to p27, 3 a current, high p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p72, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 a i lih3 v in = 15 v p60 to p63 80 a input leakage i lil1 v in = 0 v p00 to p05, p10 to p17, p20 to p27, ? a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 ?0 a i lil3 p60 to p63 ? note a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option pull-up r 1 v in = 0 v, p60 to p63 20 40 120 k ? resistor software pull-up r 2 v in = 0 v, p01 to p05, p10 to p17, p20 to p27, 15 30 90 k ? resistor p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p120 to p127, p130, p131 note when pull-up resistors are not connected to p60 to p63 (specified by the mask option), a low-level input leakage current of ?00 a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6) or port mode register 6 (pm6). at times other than this 1.5-clock interval, a ? a (max.) current flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
44 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds v dd = 5.0 v 10% note 1 3.5 7.7 ma v dd = 3.0 v 10% note 2 0.92 2.2 ma v dd = 2.0 v 10% note 2 0.47 1.2 ma v dd = 5.0 v 10% note 1 6.1 12.3 ma v dd = 3.0 v 10% note 2 1.6 3.5 ma v dd = 5.0 v 10% peripheral functions 5.5 ma operating peripheral functions 0.97 2.4 ma not operating v dd = 3.0 v 10% peripheral functions 2.1 ma operating peripheral functions 0.38 0.92 ma not operating v dd = 2.0 v 10% peripheral functions 1.1 ma operating peripheral functions 0.19 0.46 ma not operating v dd = 5.0 v 10% peripheral functions 7.5 ma operating peripheral functions 1.2 2.9 ma not operating v dd = 3.0 v 10% peripheral functions 3.3 ma operating peripheral functions 0.48 1.2 ma not operating v dd = 5.0 v 10% 46 92 a v dd = 3.0 v 10% 25 50 a v dd = 2.0 v 10% 12.5 25 a v dd = 5.0 v 10% 22.5 50 a v dd = 3.0 v 10% 3.2 13.2 a v dd = 2.0 v 10% 1.5 11.5 a v dd = 5.0 v 10% 1.0 30 a v dd = 3.0 v 10% 0.5 10 a v dd = 2.0 v 10% 0.3 10 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a dc characteristics (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) i dd1 5.0 mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 3 5.0 mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 4 5.0 mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 4 i dd2 5.0 mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 3 i dd3 32.768 khz crystal oscillation operating mode note 6 i dd4 32.768 khz crystal oscillation halt mode note 6 i dd5 xt1 = v dd stop mode when feedback resistor is used i dd6 xt1 = v dd stop mode when feedback resistor is not used parameter symbol conditions min. typ. max. unit power supply current note 5
45 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds ac characteristics (1) basic operation (t a = 40 to +85 parameter symbol conditions min. typ. max. unit t cy operating with main system v dd = 2.7 to 5.5 v 0.8 64 s clock (f xx = 2.5 mhz) note 1 2.0 64 s operating with main system 3.5 v v dd 5.5 v 0.4 32 s clock (f xx = 5.0 mhz) note 2 2.7 v v dd 3.5 v 0.8 32 s operating on subsystem clock 40 note 3 122 125 s ti00 input high-/ t tih00 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s low-level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s 2/f sam + 0.5 note 4 s ti01 input high-/ t tih01 v dd = 2.7 to 5.5 v 10 s low-level width t til01 20 s ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency 0 275 khz ti1, ti2 input t tih1 v dd = 4.5 to 5.5 v 100 ns high-/low-level t til1 1.8 s width interrupt request t inth intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 s input high-/ t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 s low-level width 2/f sam + 0.5 note 4 s intp1 to intp5, p40 to p47 v dd = 2.7 to 5.5 v 10 s 20 s reset low- t rsl v dd = 2.7 to 5.5 v 10 s level width 20 s notes 1. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is set to 00h) 2. operation with main system clock f xx = f x (when osms is set to 01h) 3. value when external clock is used. when a crystal resonator is used, it is 114 s (min.) 4. selection of f sam = f xx /2 n , f xx /32, f xx /64, and f xx /128 is possible with bits 0 and 1 (scs0, scs1) of the sampling clock selection register (scs) (when n= 0 to 4). notes 1. high-speed mode operation (when the processor clock control register (pcc) is set to 00h). 2. low-speed mode operation (when the pcc is set to 04h). 3. operation with main system clock f xx = f x /2 (when the oscillation mode select register (osms) is set to 00h) 4. operation with main system clock f xx = f x (when osms is set to 01h) 5. refer to the current flowing to the v dd0 and v dd1 pins. the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistor is not included. 6. when the main system clock operation is stopped. cycle time (minimum instruction execution time)
46 data sheet u12182ej3v0ds t cy vs. v dd (@ f xx = f x main system clock operation) t cy vs. v dd (@ f xx = f x /2 main system clock operation) 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range cycle time t cy [ s] cycle time t cy [ s]
47 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy ?50 ns address setup time t ads 0.85t cy ?50 ns address hold time t adh 50 ns time from address to data input t add1 (2.85 + 2n) t cy ?80 ns t add2 (4 + 2n) t cy ?100 ns time from rd to data input t rdd1 (2 + 2n) t cy ?100 ns t rdd2 (2.85 + 2n) t cy ?100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n) t cy ?60 ns t rdl2 (2.85 + 2n) t cy ?60 ns time from rd to wait input t rdwt1 0.85t cy ?50 ns t rdwt2 2t cy ?60 ns time from wr to wait input t wrwt 2t cy ?60 ns wait low-level width t wtl (1.15 + 2n) t cy (2 + 2n) t cy ns write data setup time t wds (2.85 + 2n) t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.85 + 2n) t cy ?60 ns delay time from astb to rd t astrd 25 ns delay time from astb to wr t astwr 0.85t cy + 20 ns delay time from rd to astb t rdast 0.85t cy ?10 1.15t cy + 20 ns at external fetch time from rd to address hold t rdadh 0.85t cy ?50 1.15t cy + 50 ns at external fetch time from rd to write data output t rdwd 40 ns time from wr to write data output t wrwd 050ns time from wr to address hold t wradh 0.85t cy 1.15t cy + 40 ns delay time from wait to rd t wtrd 1.15t cy + 40 3.15t cy + 40 ns delay time from wait to wr t wtwr 1.15t cy + 30 3.15t cy + 30 ns (2) read/write operation remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = ?0 to +85 c, v dd = 3.5 to 5.5 v)
48 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds parameter symbol conditions min. max. unit astb high-level width t asth t cy ?80 ns address setup time t ads t cy ?80 ns address hold time t adh 0.4t cy ?10 ns time from address to data input t add1 (3 + 2n) t cy ?160 ns t add2 (4 + 2n) t cy ?200 ns time from rd to data input t rdd1 (1.4 + 2n) t cy ?70 ns t rdd2 (2.4 + 2n) t cy ?70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n) t cy ?20 ns t rdl2 (2.4 + 2n) t cy ?20 ns time from rd to wait input t rdwt1 t cy ?100 ns t rdwt2 2t cy ?100 ns time from wr to wait input t wrwt 2t cy ?100 ns wait low-level width t wtl (1 + 2n) t cy (2 + 2n) t cy ns write data setup time t wds (2.4 + 2n) t cy ?60 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.4 + 2n) t cy ?20 ns delay time from astb to rd t astrd 0.4t cy ?30 ns delay time from astb to wr t astwr 1.4t cy ?30 ns delay time from rd to t rdast t cy ?10 t cy + 20 ns astb at external fetch time from rd to address t rdadh t cy ?50 t cy + 50 ns hold at external fetch time from rd to write data t rdwd 0.4t cy ?20 ns output time from wr to write data t wrwd 060ns output time from wr to address hold t wradh t cy t cy + 60 ns delay time from wait to rd t wtrd 0.6t cy + 180 2.6t cy + 180 ns delay time from wait to wr t wtwr 0.6t cy + 120 2.6t cy + 120 ns (b) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v) remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
49 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (c) when mcs = 0 or pcc2 to pcc0 000b (t a = ?0 to +85 c, v dd = 1.8 to 2.7 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy ?150 ns address setup time t ads t cy ?150 ns address hold time t adh 0.37t cy ?40 ns time from address to data input t add1 (3 + 2n) t cy ?320 ns t add2 (4 + 2n) t cy ?300 ns time from rd to data input t rdd1 (1.37 + 2n) t cy ?120 ns t rdd2 (2.37 + 2n) t cy ?120 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.37 + 2n) t cy ?20 ns t rdl2 (2.37 + 2n) t cy ?20 ns time from rd to wait input t rdwt1 t cy ?200 ns t rdwt2 2t cy ?200 ns time from wr to wait input t wrwt 2t cy ?200 ns wait low-level width t wtl (1 + 2n) t cy (2 + 2n) t cy ns write data setup time t wds (2.37 + 2n) t cy ?100 ns write data hold time t wdh 20 ns wr low-level width t wrl (2.37 + 2n) t cy ?20 ns delay time from astb to rd t astrd 0.37t cy ?50 ns delay time from astb to wr t astwr 1.37t cy ?50 ns delay time from rd to astb at t rdast t cy ?10 t cy + 20 ns external fetch time from rd to address hold t rdadh t cy ?50 t cy + 50 ns at external fetch time from rd to write data output t rdwd 0.37t cy ?40 ns time from wr to write data output t wrwd 0 120 ns time from wr to address hold t wradh t cy t cy + 120 ns delay time from wait to rd t wtrd 0.63t cy + 350 2.63t cy + 350 ns delay time from wait to wr t wtwr 0.63t cy + 240 2.63t cy + 240 ns remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
50 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) delay time from sck0 to so0 output (3) serial interface (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 ?50 ns t kcy1 /2 ?100 ns t sik1 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of the sck0 and so0 output lines. parameter symbol conditions min. typ. max. unit t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns t sik2 2.0 v v dd 5.5 v 100 ns 150 ns t ksi2 400 ns t kso2 c = 100 pf note v dd = 2.0 to 5.5v 300 ns 500 ns t r2 , t f2 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function sck0 cycle time sck0 high-/low-level width si0 setup time (to sck0 ) si0 hold time (from sck0 ) delay time from sck0 to so0 output sck0 rise/fall time (ii) 3-wire serial i/o mode (sck0... external clock input) note c is the load capacitance of the so0 output line.
51 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (iv) 2-wire serial i/o mode (sck0... internal clock input) parameter symbol conditions min. typ. max. unit t kcy4 2.7 v v dd 5.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns t kh4 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1,300 ns 2,100 ns t kl4 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns t sik4 v dd = 2.0 to 5.5 v 100 ns 150 ns t ksi4 t kcy4 /2 ns t kso4 4.5 v v dd 5.5 v 0 300 ns 2.0 v v dd < 4.5 v 0 500 ns 0 800 ns t r4 , t f4 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function r = 1 k ? , c = 100 pf note (iii) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 r = 1 k ? , 2.7 v v dd 5.5 v 1,600 ns c = 100 pf note 2.0 v v dd 2.7 v 3,200 ns 4,800 ns sck0 high-level width t kh3 v dd = 2.7 to 5.5 v t kcy3 /2 ?160 ns t kcy3 /2 ?190 ns sck0 low-level width t kl3 v dd = 4.5 to 5.5 v t kcy3 /2 ?50 ns t kcy3 /2 ?100 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 300 ns (to sck0 ) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 500 ns sb0, sb1 hold time t ksi3 600 ns (from sck0 ) ns delay time from sck0 t kso3 0 300 ns to sb0, sb1 output note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 ) sb0, sb1 hold time (from sck0 ) delay time from sck0 to sb0, sb1 output sck0 rise/fall time
52 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (v) sbi mode (sck0... internal clock output) ( pd78005x only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3,200 ns 4,800 ns sck0 high-/low-level t kh5 , t kl5 4.5 v v dd 5.5 v t kcy5 /2 ?50 ns width t kcy5 /2 ?150 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi5 t kcy5 /2 ns (from sck0 ) delay time from sck0 t kso5 r = 1 k ? , v dd = 4.5 to 5.5 v 0 250 ns to sb0, sb1 output c = 100 pf note 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy5 ns sck0 from sb0, sb1 t sbk t kcy5 ns sb0, sb1 high-level width t sbh t kcy5 ns sb0, sb1 low-level width t sbl t kcy5 ns note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) sbi mode (sck0... external clock input) ( pd78005x only) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3,200 ns 4,800 ns sck0 high-/low-level t kh6 , t kl6 4.5 v v dd 5.5 v 400 ns width 2.0 v v dd < 4.5 v 1,600 ns 2,400 ns sb0, sb1 setup time t sik6 4.5 v v dd 5.5 v 100 ns (to sck0 ) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 ) delay time from sck0 t kso6 r = 1 k ? , v dd = 4.5 to 5.5 v 0 300 ns to sb0, sb1 output c = 100 pf note 0 1,000 ns sb0, sb1 from sck0 t ksb t kcy6 ns sck0 from sb0, sb1 t sbk t kcy6 ns sb0, sb1 high-level width t sbh t kcy6 ns sb0, sb1 low-level width t sbl t kcy6 ns sck0 rise/fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
53 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (vii) i 2 c bus mode (scl ... internal clock output) ( pd7800xy only) parameter symbol conditions min. typ. max. unit scl cycle time t kcy7 r = 1 k ? , 2.7 v v dd 5.5 v 10 s c = 100 pf note 2.0 v v dd < 2.7 v 20 s 30 s scl high-level width t kh7 v dd = 2.7 to 5.5 v t kcy7 ?160 ns t kcy7 ?190 ns scl low-level width t kl7 v dd = 4.5 to 5.5 v t kcy7 ?50 ns t kcy7 ?100 ns sda0, sda1 setup time t sik7 2.7 v v dd 5.5 v 200 ns (to scl ) 2.0 v v dd < 2.7 v 300 ns 400 ns sda0, sda1 hold time t ksi7 0ns (from scl ) delay time from scl t kso7 4.5 v v dd 5.5 v 0 300 ns to sda0, sda1 output 2.0 v v dd < 4.5 v 0 500 ns 0 600 ns sda0, sda1 from scl or t ksb 200 ns sda0, sda1 from scl scl from sda0, sda1 t sbk v dd = 2.0 to 5.5 v 400 ns 500 ns sda0, sda1 high-level width t sbh 500 ns note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. (viii) i 2 c bus mode (scl ... external clock input) ( pd78005xy only) parameter symbol conditions min. typ. max. unit scl cycle time t kcy8 1,000 ns scl high-/low-level width t kh8 v dd = 2.0 to 5.5 v 400 ns t kl8 600 ns sda0, sda1 setup time t sik8 v dd = 2.0 to 5.5 v 200 ns (to scl ) 300 ns sda0, sda1 hold time t ksi8 0ns (from scl ) delay time from scl t kso8 r = 1 k ? , 4.5 v v dd 5.5 v 0 300 ns to sda0, sda1 output c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 0 600 ns sda0, sda1 from scl or t ksb 200 ns sda0, sda1 from scl scl from sda0, sda1 t sbk v dd = 2.0 to 5.5 v 400 ns 500 ns sda0, sda1 high-level width t sbh v dd = 2.0 to 5.5 v 500 ns 800 ns scl rise/fall time t r8 when using external device expansion 160 ns function t f8 when not using external device 1 s expansion function note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines.
54 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1...internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck1 high/low-level width t kh9 , t kl9 v dd = 4.5 to 5.5 v t kcy9 /2 ?50 ns t kcy9 /2 ?100 ns si1 setup time (to sck1 )t sik9 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time (from sck1 )t ksi9 400 ns delay time from sck1 to so1 t kso9 c = 100 pf note 300 ns output (ii) 3-wire serial i/o mode (sck1...external clock input) note c is the load capacitance of the sck1 and so1 output lines. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck1 high/low-level width t kh10 ,t kl10 4.5 v v dd 5.5 v 400 ns 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns si1 setup time (to sck1 )t sik10 v dd = 2.0 to 5.5 v 100 ns 150 ns si1 hold time (from sck1 )t kis10 400 ns delay time from sck1 to so1 t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output 500 ns sck1 rise/fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line.
55 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1...internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck1 high-/low-level width t kh11 ,t kl11 v dd = 4.5 to 5.5 v t kcy11 /2 ?50 ns t kcy11 /2 ?100 ns si1 setup time (to sck1 )t sik11 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time (from sck1 )t ksi11 400 ns delay time from sck1 to so1 t kso11 c = 100 pf note 300 ns output stb from sck1 t sbd t kcy11 /2 ?100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw 2.7 v v dd < 5.5 v t kcy11 ?30 t kcy11 + 30 ns 2.0 v < v dd < 2.7 v t kcy11 ?60 t kcy11 + 60 ns t kcy11 ?90 t kcy11 + 90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 200 ns 300 ns sck1 from busy inactive t sps 2t kcy11 ns note c is the load capacitance of the sck1 and so1 output lines.
56 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1...external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck1 high-/low-level width t kh12, 4.5 v v dd 5.5 v 400 ns t kl12 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns si1 setup time (to sck1 )t sik12 v dd = 2.0 to 5.5 v 100 ns 150 ns si1 hold time (from sck1 )t ksi12 400 ns delay time from sck1 to so1 t kso12 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output 500 ns sck1 rise/fall time t r12, t f12 when using external device 160 ns expansion function when not using external device 1,000 ns expansion function note c is the load capacitance of the so1 output line.
57 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2...internal clock output) parameter symbol conditions min. typ. max. unit sck2 cycle time 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck2 high-/low-level width v dd = 4.5 to 5.5 v t kcy13 /2 ?50 ns t kcy13 /2 ?100 ns si2 setup time (to sck2 ) 4.5 v v dd 5.5 v 100 ns 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si2 hold time (from sck2 ) 400 ns delay time from sck2 to so2 c = 100 pf note 300 ns output note c is the load capacitance of the so2 output line. t kcy13 t kh13 , t kl13 t sik13 t ksi13 t kso13 (ii) 3-wire serial i/o mode (sck2...external clock input) parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy14 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns sck2 high-/low-level width t kh14, 4.5 v v dd 5.5 v 400 ns t kl14 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns si2 setup time (to sck2 )t sik14 v dd = 2.0 to 5.5 v 100 ns 150 ns si2 hold time (from sck2 )t ksi14 400 ns delay time from sck2 to so2 t kso14 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output 500 ns sck2 rise/fall time t r14, other than below 160 ns t f14 v dd = 4.5 to 5.5 v 1 s when not using external device expansion function note c is the load capacitance of the so2 output line.
58 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78,125 bps 2.7 v v dd < 4.5 v 39,063 bps 2.0 v v dd < 2.7 v 19,531 bps 9,766 bps (iv) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck cycle time t kcy15 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1,600 ns 2.0 v v dd < 2.7 v 3,200 ns 4,800 ns asck high-/low-level width t kh15, 4.5 v v dd 5.5 v 400 ns t kl15 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1,600 ns 2,400 ns transfer rate 4.5 v v dd 5.5 v 39,063 bps 2.7 v v dd < 4.5 v 19,531 bps 2.0 v v dd < 2.7 v 9,766 bps 6,510 bps asck rise/fall time t r15, v dd = 4.5 to 5.5 v, 1,000 ns t f15 when not using external device expansion function. 160 ns
59 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y ac timing measurement points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input 1/f ti1 t til1 t tih1 ti1, ti2 t til00 , t til01 t tih00 , t tih01 ti00, ti01 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement
60 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds read/write operation external fetch (no wait): external fetch (wait insertion): t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address operation code t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 higher 8-bit address operation code lower 8-bit address
61 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y external data access (no wait): external data access (wait insertion): t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwd lower 8-bit address t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wdwr t astwr t wradh higher 8-bit address write data read data t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd lower 8-bit address
62 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y 3-wire serial i/o mode: 2-wire serial i/o mode: serial transfer timing t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 t sikm t ksim t ksom input data output data t rn t fn t kso3, 4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksi3, 4 sb0, sb1 t f4 t r4
63 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y sbi mode (bus release signal transfer): sbi mode (command signal transfer): i 2 c bus mode : t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t sbl t sbh t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 t sik5, 6 t kcy5,6 t kl5, 6 t kh5, 6 sck0 t ksb t sbk t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 scl sda0, sda1 t klm t sbh t sikm t ksb t ksb t khm t kcym t r8 t f8 t sikm t ksom t sbk t ksim m = 7, 8
64 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing): uart mode (external clock input): t sbw t sbd t kcy11, 12 t kh11, 12 t ksi11, 12 t sik11, 12 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r12 t kl11, 12 t f12 t kso11, 12 t kcy15 t kh15 t kl15 t f15 t r15 asck note the signal is not actually driven low here; it is shown as such to indicate the timing. t bys sck1 t sps busy (active hi g h) 789 note 10 note 10 + n note 1 t byh
65 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y a/d converter characteristics (except pd780058) (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 1.8 v av ref0 < 2.7 v +1.4 %fsr 2.7 v av ref0 < 5.5 v +0.6 %fsr conversion time t conv1 1.8 v av ref0 < 2.7 v 40 100 s t conv2 2.7 v av ref0 < 5.5 v 16 100 s analog input voltage v ian av ss av ref0 v reference voltage av ref0 1.8 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 a when a/d converter is not operating note 3 03 a notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value (%fsr). 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. a/d converter characteristics ( pd780058) (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 1 +0.6 %fsr conversion time t conv 16 100 s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 v dd v av ref0 current i ref0 when a/d converter is operating note 2 500 1,500 a when a/d converter is not operating note 3 03 a notes 1. excludes quantization error ( 1/2 lsb). this value is indicated as a ratio to the full-scale value (%fsr). 2. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 1. 3. the current flowing to the av ref0 pin when bit 7 (cs) of the a/d converter mode register (adm) is 0. caution the operating voltage range of the a/d converter and d/a converter of the pd780058 is v dd = 2.7 to 5.5 v.
66 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y parameter symbol conditions min. typ. max. unit resolution 8bit overall error r = 2 m ? note 1 1.2 % r = 4 m ? note 1 0.8 % r = 10 m ? note 1 0.6 % settling time c = 30 pf note 1 av ref1 = 1.8 to 2.7 v 10 s 15 s output resistance r o note 2 8k ? analog reference voltage av ref1 1.8 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k ? d/a converter characteristics (except pd780058) (t a = ?0 to +85 c, v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value setting registers 0, 1 parameter symbol conditions min. typ. max. unit resolution 8 bit overall error r = 2 m ? note 1 1.2 % r = 4 m ? note 1 0.8 % r = 10 m ? note 1 0.6 % settling time c = 30 pf note 1 15 s output resistance r o note 2 8k ? analog reference voltage av ref1 2.7 v dd v av ref1 current i ref1 note 2 2.5 ma resistance between av ref1 and av ss r airef1 dacs0, dacs1 = 55h note 2 48 k ? d/a converter characteristics ( pd780058) (t a = ?0 to +85 c, v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0 and dacs1: d/a conversion value setting registers 0, 1 caution the operating voltage range of the a/d converter and d/a converter of the pd780058 is v dd = 2.7 to 5.5 v.
67 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) note selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts). parameter symbol conditions min. typ. max. unit data retention supply v dddr 1.8 5.5 v voltage data retention supply i dddr v dddr = 1.8 v 0.1 10 a current subsystem clock stop and feed-back resistor disconnected release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt request note ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop instruction execution stop mode data retension mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
68 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y interrupt request input timing reset input timing t intl t inth intp0 to intp5 t rsl reset
69 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y 13. characteristics curves (reference values) v dd vs i dd (f x = 5.0 mhz, f xx = 2.5 mhz) 10 1 0.1 0.01 0.001 2 0 34567 supply voltage v dd [v] (t a = 25 c) supply current i dd [ma] pcc = 00h pcc = b0h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillating, xt1 oscillating) halt (x1 stopped, xt1 oscillating)
70 data sheet u12182ej3v0ds pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y v dd vs i dd (f x = f xx = 5.0 mhz) 10 1 0.1 0.01 0.001 2 0 34567 supply voltage v dd [v] supply current i dd [ma] pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillating, xt1 oscillating) approximately the same curve pcc = b0h halt (x1 stopped, xt1 oscillating)
71 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 14. package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
72 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 60 41 40 21 61 80 120 80-pin plastic tqfp (fine pitch) (12x12) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 14.0 0.2 12.0 0.2 1.25 14.0 0.2 c 12.0 0.2 0.10 i j h0.22 0.05 0.5 (t.p.) k 1.0 0.2 f1.25 m 0.145 0.05 1.0 0.05 p q n0.10 0.1 0.05 l0.5 0.2 s80gk-50-9eu-1 s 1.2 max. r3 + 7 ? 3 m s s n j detail of lead end c d a b r k m l p i s q g f h
73 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds 15. recommended soldering conditions the pd78005x and 78005xy should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 15-1. surface mounting type soldering conditions (1/2) pd780053gc- -8bt: 80-pin plastic qfp (14 14) pd780054gc- -8bt: 80-pin plastic qfp (14 14) pd780055gc- -8bt: 80-pin plastic qfp (14 14) pd780056gc- -8bt: 80-pin plastic qfp (14 14) pd780058gc- -8bt: 80-pin plastic qfp (14 14) pd780053ygc- -8bt: 80-pin plastic qfp (14 14) pd780054ygc- -8bt: 80-pin plastic qfp (14 14) pd780055ygc- -8bt: 80-pin plastic qfp (14 14) pd780056ygc- -8bt: 80-pin plastic qfp (14 14) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: twice or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: twice or less wave soldering soldering bath temperature: 260 c or less, time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
74 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds table 15-1. surface mounting type soldering conditions (2/2) pd780053gk- -9eu: 80-pin plastic tqfp (12 12) pd780054gk- -9eu: 80-pin plastic tqfp (12 12) pd780055gk- -9eu: 80-pin plastic tqfp (12 12) pd780056gk- -9eu: 80-pin plastic tqfp (12 12) pd780058gk- -9eu: 80-pin plastic tqfp (12 12) pd780053ygk- -9eu: 80-pin plastic tqfp (12 12) pd780054ygk- -9eu: 80-pin plastic tqfp (12 12) pd780055ygk- -9eu: 80-pin plastic tqfp (12 12) pd780056ygk- -9eu: 80-pin plastic tqfp (12 12) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), ir35-107-2 count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), vp15-107-2 count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering partial heating pin temperature: 300 c or less, time: 3 seconds max. (per pin row) note after opening the dry pack, store it below 25 c and 65% rh for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
75 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds appendix a. development tools the following development tools are available for system development using the pd780058 and 780058y subseries. also, refer to (5) cautions on using development tools. (1) language processing software ra78k0 assembler package common to the 78k/0 series cc78k0 c compiler package common to the 78k/0 series df780058 device file for the pd780058, 780058y subseries cc78k0-l c compiler library source file common to the 78k/0 series (2) flash memory writing tools flashpro iii (part number: dedicated flash programmer for microcontrollers incorporating flash memory fl-pr3, pg-fl3) fa-80gc-8bt adapter for flash memory writing fa-80gk-9eu (3) debugging tools when using the ie-78k0-ns in-circuit emulator ie-78k0-ns in-circuit emulator common to the 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board to enhance and expand the functions of the ie-78k0-ns ie-70000-98-if-c interface adapter used when a pc-9800 series pc (except notebook types) is used as the host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable used when a pc-9800 series notebook-types pc is used as the host machine (pcmcia socket supported) ie-70000-pc-if-c adapter necessary when an ibm pc/at tm or compatible is used as the host machine (isa bus supported) ie-70000-pci-if-a interface adapter necessary when using a pc with pci bus as the host machine ie-780308-ns-em1 emulation board common to the pd780308 subseries np-80gc emulation probe for 80-pin plastic qfp (gc-8bt type) np-80gk emulation probe for 80-pin plastic tqfp (gk-9eu type) tgk-080sdw conversion adapter to connect the np-80gk and a target system board 80-pin plastic tqfp (gk-9eu type) can be mounted ev-9200gc-80 socket to be mounted on a target system board made for 80-pin plastic qfp (gc-8bt type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to the 78k/0 series df780058 device file for the pd780058, 780058y subseries
76 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds when using the ie-78001-r-a in-circuit emulator ie-78001-r-a in-circuit emulator common to the 78k/0 series ie-70000-98-if-c adapter used when pc-9800 series pc (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as host machine (isa bus supported) ie-78000-r-sv3 interface adapter and cable used when ews is used as the host machine ie-780308-ns-em1 emulation board common to the pd780308 subseries ie-780308-r-em ie-78k0-r-ex1 emulation probe conversion board necessary when using the ie-780308-ns-em1 on the ie-78001-r-a ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ep-78054gk-r emulation probe for 80-pin plastic tqfp (gk-9eu type) tgk-080sdw conversion adapter to connect the ep-78054gk-r and a target system on which an 80- pin plastic tqfp (gk-9eu type) can be mounted ev-9200gc-80 socket to be mounted on a target system board made for 80-pin plastic qfp (gc-8bt type) id78k0 integrated debugger for ie-78001-r-a sm78k0 78k/0 series common system simulator df780058 device file for the pd780058, 780058y subseries (4) real-time os rx78k0 real-time os for the 78k/0 series mx78k0 os for the 78k/0 series
77 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds (5) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780058. the cc78k0 and rx78k0 are used in combination with the ra78k0 and df780058. the fl-pr3, fa-80gc-8bt, fa80gk-9eu, np-80gc, and np-80gk are products of naito densei machida mfg. co., ltd. (tel: +81-44-822-3813). tgk-080sdw is a product made by tokyo eletech corporation. for further information, contact daimaru kogyo, ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6-244-6672) for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e). the host machine and os suitable for each software are as follows: host machine [os] pc ews pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatibles sparcstation tm [sunos tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k0 note cc78k0 note id78k0-ns id78k0 ? sm78k0 rx78k0 note mx78k0 note note dos-based software
78 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780058, 780058y subseries user? manual u12013e pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, this document 780056y data sheet pd78f0058, 78f0058y data sheet u12092e 78k/0 series user? manual instruction u12326e documents related to development tools (user? manuals) document name document no. ra78k0 assembler package operation u11802e assembly language u11801e structured assembly u11789e language cc78k0 c compiler operation u11517e language u11518e ie-78k0-ns u13731e ie-78001-r-a to be prepared ie-780308-ns-em1 u13304e ie-780308-r-em u11362e ep-78230 eeu-1515 ep-78054gk-r sm78k0s, sm78k0 system simulator ver.2.10 or later operation u14611e windows based sm78k series system simulator ver.2.10 or later external part user open u15006e interface specifications id78k0-ns integrated debugger ver.2.00 or later operation u14379e windows based id78k0 integrated debugger windows based reference u11539e guide u11649e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. appendix b. related documents
79 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds documents related to embedded software (user? manuals) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamental u12257e other related documents document name document no. semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
80 pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y data sheet u12182ej3v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided thst the system conforms to the i 2 c standard specification as defined by philips. fip and iebus are trademarks of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
81 ? ? ? ? ? ?
pd780053, 780054, 780055, 780056, 780058, 780053y, 780054y, 780055y, 780056y the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of november, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a pa rticular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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